1. Field of the Invention
The present invention relates to solid-state image pickup devices, semiconductor devices, and camera systems. More particularly, the present invention relates to a solid-state image pickup device, a semiconductor device, and a camera system including regularly arranged elements (e.g., photoelectric conversion elements).
2. Description of the Related Art
Recently, solid-state image pickup elements, such as complementary metal oxide semiconductor (CMOS) image sensors, have been widely used as image input devices of image capturing apparatuses included in various mobile terminals, such as mobile phones, and of image capturing apparatuses, such as digital still cameras or digital video cameras (see, for example, Japanese Unexamined Patent Application Publication No. 10-126697).
FIG. 4 is a schematic diagram illustrating a CMOS image sensor. The CMOS image sensor includes an pixel array 202 in which many pixels 201 each including a photoelectric conversion element are arranged in a matrix form and a vertical scanning circuit 203 for selecting each pixel in the pixel array 202 on a row-by-row basis and controlling a shutter operation and a readout operation of the pixel. The CMOS image sensor also includes a column signal processing unit 204 for reading out a signal from the pixel array 202 and performing predetermined image processing (e.g., correlated double sampling (CDS) processing, auto gain control (AGC) processing, and analog/digital conversion processing) on a column-by-column basis. Furthermore, the CMOS image sensor includes a horizontal scanning circuit 206 for selecting the signal of the column signal processing unit 204 one by one and supplying the selected signal to a horizontal signal line 205, and a data signal processing unit 207 for converting the signal fed from the horizontal signal line 205 into an intended output data format. The CMOS image sensor also includes a timing generator 208 for supplying various pulse signals used in an operation of each unit on the basis of a reference clock. Herein, the CDS processing indicates processing for eliminating a fixed pattern noise resulting from variance in thresholds of pixel transistors. The AGC processing indicates auto gain control processing.
As shown in FIG. 5, each pixel 201 included in the pixel array 202 has a photoelectric conversion element (e.g., a photodiode) 101, a transfer transistor 102, a reset transistor 103, an amplifying transistor 104, and a selecting transistor 105. FIG. 5 shows an example circuit that uses N-channel MOS (NMOS) transistors as the transistors 102-105.
The transfer transistor 102 is connected between a cathode of the photodiode 101 and a floating diffusion (FD) portion 106. A gate of the transfer transistor 102 is connected to a transfer control line 111 that is supplied with a transfer gate pulse TG. A drain of the reset transistor 103 is connected to a power supply Vdd, whereas a source and a gate thereof are connected to the FD portion 106 and a reset control line 112 that is supplied with a reset pulse RS, respectively.
A gate of the amplifying transistor 104 is connected to the FD portion 106, whereas a drain and a source thereof are connected to the power supply Vdd and a drain of the selecting transistor 105, respectively. A gate of the selecting transistor 105 is connected to a selection control line 113 that is supplied with a selection pulse SEL, whereas a source thereof is connected to a vertical signal line 216. The vertical signal line 216 is connected to a constant-current source 217 for supplying constant current thereto and is also connected to the column signal processing unit 204.
FIG. 6 is a schematic diagram showing a section of a pixel excluding the amplifying transistor 104 and the selecting transistor 105.
N-type diffusion regions 132, 133, and 134 are formed on a surface of a P-type substrate 131. Additionally, a gate 135 is formed at an upper area between the N-type diffusion regions 132 and 133 on the P-type substrate 131. Furthermore, a gate 136 is formed at an upper area between the N-type diffusion regions 133 and 134. The gates 135 and 136 are formed on the substrate through a gate oxide film (SiO2), not shown.
According to a correspondence between FIGS. 5 and 6, the photodiode 101 is formed by PN junction between the P-type substrate 131 and the N-type diffusion region 132. The transfer transistor 102 is formed by the N-type diffusion region 132, the N-type diffusion region 133, and the gate 135 provided therebetween. The reset transistor 103 is formed by the N-type diffusion region 133, the N-type diffusion region 134, and the gate 136 provided therebetween.
The N-type diffusion region 133 serves as the FD portion 106 and is electrically connected to the gate of the amplifying transistor 104. The N-type diffusion region 134 serving as the drain of the reset transistor 103 is supplied with a power supply potential Vdd. The upper surface of the P-type substrate 131 excluding the photodiode 101 is covered with a light-shielding layer 137.
An operation of a circuit of the pixel 201 will now be described with reference to the sectional view shown in FIG. 6 and a waveform chart shown in FIG. 7.
As shown in FIG. 6, in response to illumination of the photodiode 101 with light, pairs of electrons (−) and positive holes (+) are induced (photoelectric conversion) in accordance with intensity of the light. Referring to FIG. 7, a selection pulse SEL is applied to the gate of the selecting transistor 105 at time T1. At the same time, a reset pulse RS is applied to the gate of the reset transistor 103. As a result, the reset transistor 103 conducts, which resets the FD portion 106 to a power supply potential Vdd at time T2.
In response to resetting of the FD portion 106, a potential of the reset FD portion 106 is output to the vertical signal line 216 through the amplifying transistor 104 as a reset level Vn. This reset level Vn corresponds to a noise component unique to the pixel 201. The reset pulse RS becomes active (a “high (H) level”) during a predetermined period (between the time T1 and the time T3). The FD portion 106 is kept in the reset state even after the reset pulse RS shifts into a non-active state (i.e., a “low (L) level”) from the active state. The period during which the FD portion 106 is in the reset state corresponds to a reset period.
A transfer gate pulse TG is applied to the gate of the transfer transistor 102 at time T4 with the selection signal SEL being active, in response to which the transfer transistor 102 conducts. The photodiode 101 then performs photoelectric conversion. An accumulated signal charge is transferred to the FD portion 106. As a result, the potential of the FD portion 106 changes in accordance with an amount of the signal charge (between the time T4 and time T5). At this time, the potential of the FD portion 106 is output to the vertical signal line 216 through the amplifying transistor 104 as a signal level Vs (during a signal read period). A difference RSI1 between the signal level Vs and the reset level Vn corresponds to a noise-component-free pixel signal level.
Since more charges are generally accumulated in the photodiode 101 during the reset period when an image of a brighter object is captured than when an image of a darker object is captured, the difference RSI1 on the vertical signal line 216 becomes larger.
Since solid-state image pickup elements, such as CMOS image sensors, use photoexcitation current of a nanoampere (nA) order as a signal, leakage current due to a defect of a semiconducting crystal greatly affects. Accordingly, manufacturing processes for reducing the leakage current, such as a process for manufacturing elements under a more highly cleaned environment than that for general integrated circuits and a process for employing various kinds of annealing processing to reduce a crystal defect, are adopted. However, a small number of pixels having large leakage current or having low luminous sensitivity still exist. It may be difficult to eliminate these pixels. Solid-state image pickup elements having such pixels are those having so-called defective pixels.
Even if there are solid-state image pickup elements having defective pixels, substantially defect-free images can be obtained by correcting the images including signals from the defective pixels on the basis of output signals acquired by pixels neighboring the defective pixels.
Accordingly, in general, CMOS image sensors output image data including signals of defective pixels and perform signal processing on the output image data to correct an image including the signals output from the defective pixels. Japanese Unexamined Patent Application Publication No. 4-160883 discloses a technique for connecting a nonvolatile memory storing position information of a defective pixel to a timing generator and replacing a value output from the defective pixel with a predetermined value determined based on a value of a pixel neighboring the defective pixel at the position of the defective pixel of an image pickup element.